AI for Science with GPT-6 Astra: Thermal Design and Electrothermal Analysis of 2D CFET
Authors: Min-Hui Kim, Khushi Sharma, Sarah Zhang, Ye Wang
Organizations: Graduate School of Semiconductor Materials and Devices, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea · Materials Science and Engineering, National University of Singapore, Singapore · Materials Science and Engineering, Cornell University, Ithaca, NY, USA · Department of Applied Physics and Science Education, Technische Universiteit Eindhoven, Eindhoven, The Netherlands
Thermal optimization of 2D CFET inverters requires testing structural proposals against their electrical costs. We examine these research tasks using an AI agent workflow within a supplied electrothermal model. At 12 nm, Astra selects a redistributed source-interconnect geometry, while a coordinating agent proposes a substrate-directed heat-removal path. The combined design reduces peak temperature rise by 1.67 K at fixed metal volume and 20 μW. A subsequent metal-resistance sensitivity gives about 0.6-K inverter cooling alongside a 2% nFET on-current loss. Effective contact-length scaling further shows that lower temperature can accompany higher thermal resistance when current falls. Reproduction identifies agreeing implementations and retains a 104.95-K failure for diagnosis. These results show that an AI scientist workflow can propose thermal structures, test them under common constraints, and quantify their electrical cost.
Figures & tables
Fig. 1: Agent workflow within a supplied model. Astra plans the interconnect search; the coordinating agent interprets the trend and proposes the via extension. Tool calls execute the tests; separate reruns check code consistency.
Fig. 2: Thermal design and electrical cost. (a) Selected device at 20 μ W, Pn/Pp=2 , Rcm=5 m 2 K/GW. At Lg=12 nm, (b) upper width varies at fixed metal volume or fixed lower width; (c) effective contact length varies. Changes are relative to wn=wp=8 nm, Lc=20 nm. Rth,peak uses fixed 20 μ W; self-heated Ion,n includes metal resistance at VGS=VDS=0.7 V.
Fig. 3: DC inverter response without metal resistance at VDD=0.7 V. (a) Voltage transfer characteristics, (b) DC power and (c) peak lattice temperature for baseline interconnects. Colors denote gate length; solid curves include self-heating, dashed curves are isothermal at 300 K. (d) Selected 12-nm device sections at y=0 under two static biases, with a common temperature scale and emphasized channels.
Structure
ΔTmax (K)
Reduction (K)
Baseline
141.63
0.00
Redistributed interconnect
140.75
0.88
Substrate-directed path
140.83
0.80
Combined
139.96
1.67
TABLE I: Thermal performance of design stages on a common mesh
Model / effort label
eT (K)
eC (pp)
Status
GPT-6 / Light a
0 (ref.)
0 (ref.)
Reference
GPT-6 Astra / Ultra b
1.34e-12
3.20e-13
Pass
Claude Fable 5.1 / high
4.26e-13
2.42e-13
Pass
Claude Opus 5 / high (A)
4.98e-10
2.88e-10
Pass
Claude Opus 5 (B)
4.26e-13
2.42e-13
Pass
GPT-5.6 Sol / max
4.98e-10
2.88e-10
Pass
TABLE II: Cross-agent reproduction of the fixed thermal reference cases
Parameter
GPT study
Claude baseline → C4
Sheets per tier (total)
4 (8)
1 (2)
Lg,Lh,W (nm)
12, 16, 40
20, 30, 50
tn,tp (nm)
0.65, 0.70
0.65, 0.65
Gate dielectric (nm)
1
3 (HfO 2 )
Within-tier gap (nm)
6
Not applicable
Inter-tier gap (nm)
20
26
TABLE III: Device parameters for the two design studies
High-density through-substrate vias (TSVs) enable 2.5D/3D heterogeneous integration but introduce significant signal-integrity and thermal-reliability challenges due to electrical coupling, insertion loss, and self-heating. Conventional full-wave finite-element method (FEM) simulations provide high accuracy but become computationally prohibitive for large design-space exploration. This work presents a scalable electro--thermal modeling and optimization framework that combines physics-informed analytical modeling, graph neural network (GNN) surrogates, and full-wave sign-off validation. A multi-conductor analytical model computes broadband S-parameters and effective anisotropic thermal conductivities of TSV arrays, achieving 5%--10% relative Frobenius error (RFE) across array sizes up to 15×15. A physics-informed GNN surrogate (TSV-PhGNN), trained on analytical data and fine-tuned with HFSS simulations, generalizes to larger arrays with mean RFE below 5% in-distribution. The surrogate is integrated into a multi-objective Pareto optimization framework targeting reflection coefficient, insertion loss, worst-case crosstalk (NEXT/FEXT), and effective thermal conductivity. Millions of TSV configurations can be explored within minutes, enabling exhaustive layout and geometric optimization that would be infeasible using FEM alone. Final designs are validated with Ansys HFSS and Mechanical, showing strong agreement. The proposed framework enables rapid electro--thermal co-design of TSV arrays while reducing per-design evaluation time by more than six orders of magnitude.
Mohamed Gharib, Leonid Popryho, Inna Partin-Vaisband
Department of Electrical and Computer Engineering, University of Illinois Chicago, Chicago, IL 60607, USA
Accurate thermal analysis of heterogeneous 2.5D/3D-IC packages is essential yet computationally prohibitive. A single full-package FEM simulation can take hours, while AI-based surrogates treat the entire stack as a monolithic prediction target and must be retrained whenever the die count or topology changes. To address this limitation, this work proposes Domain-Decomposed AI-Accelerated Iterative Solver for Thermal Analysis (DAIST), a composable thermal solver that decomposes the global package simulation into block-level subdomain problems, replaces subdomain solvers with neural operators, and couples them through iterative exchanges of interfacial temperature and heat flux. This local-to-global architecture eliminates the topology lock-in of monolithic models: block-level neural operators can be directly reused in unseen package assemblies without retraining. The iterative coupling strategy further provides a controllable accuracy-runtime tradeoff, where the iteration budget can be adjusted to trade accuracy for runtime. Evaluated on a multi-chiplet system and an advanced packaging system, DAIST achieves up to 178× speedup over traditional FEM solvers with mean temperature errors of 0.068% and 0.323%, respectively, while demonstrating cross-topology reuse of block-level models across structurally distinct package assemblies.
Rapid growth in artificial intelligence (AI) workloads is driving up data center power densities, increasing the need for advanced thermal management. Direct-to-chip liquid cooling can remove heat efficiently at the source, but many cold plate channel layouts remain heuristic and are not optimized for the strongly non-uniform temperature distribution of modern heterogeneous packages. This work presents a generative design framework for synthesizing cooling channel geometries for the NVIDIA GB200 Grace Blackwell Superchip. A physics-based finite-difference thermal model provides rapid steady-state temperature predictions and supplies spatial thermal feedback to a constrained reaction-diffusion process that generates novel channel topologies while enforcing inlet/outlet and component constraints. By iterating channel generation and thermal evaluation in a closed loop, the method naturally redistributes cooling capacity toward high-power regions and suppresses hot-spot formation. Compared with a baseline parallel channel design, the resulting channels achieve more than a 5 degree Celsius reduction in average temperature and over 35 degree Celsius reduction in maximum temperature. Overall, the results demonstrate that coupling generative algorithms with lightweight physics-based modeling can significantly enhance direct-to-chip liquid cooling performance, supporting more sustainable scaling of AI computing.