AI for Science with GPT-6 Astra: Thermal Design and Electrothermal Analysis of 2D CFET

Min-Hui Kim; Khushi Sharma; Sarah Zhang; Ye Wang

cond-mat.mtrl-sciSep 15, 2026

AI for Science with GPT-6 Astra: Thermal Design and Electrothermal Analysis of 2D CFET

Authors: Min-Hui Kim, Khushi Sharma, Sarah Zhang, Ye Wang

Organizations: Graduate School of Semiconductor Materials and Devices, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea · Materials Science and Engineering, National University of Singapore, Singapore · Materials Science and Engineering, Cornell University, Ithaca, NY, USA · Department of Applied Physics and Science Education, Technische Universiteit Eindhoven, Eindhoven, The Netherlands

Abstract

Thermal optimization of 2D CFET inverters requires testing structural proposals against their electrical costs. We examine these research tasks using an AI agent workflow within a supplied electrothermal model. At 12 nm, Astra selects a redistributed source-interconnect geometry, while a coordinating agent proposes a substrate-directed heat-removal path. The combined design reduces peak temperature rise by 1.67 K at fixed metal volume and 20 μW. A subsequent metal-resistance sensitivity gives about 0.6-K inverter cooling alongside a 2% nFET on-current loss. Effective contact-length scaling further shows that lower temperature can accompany higher thermal resistance when current falls. Reproduction identifies agreeing implementations and retains a 104.95-K failure for diagnosis. These results show that an AI scientist workflow can propose thermal structures, test them under common constraints, and quantify their electrical cost.

Figures & tables

Fig. 1: Agent workflow within a supplied model. Astra plans the interconnect search; the coordinating agent interprets the trend and proposes the via extension. Tool calls execute the tests; separate reruns check code consistency.

Fig. 2: Thermal design and electrical cost. (a) Selected device at 20 $\mu$ W, $P_{n}/P_{p}=2$ , $R_{cm}=5$ m 2 K/GW. At $L_{g}=12$ nm, (b) upper width varies at fixed metal volume or fixed lower width; (c) effective contact length varies. Changes are relative to $w_{n}=w_{p}=8$ nm, $L_{c}=20$ nm. $R_{th,peak}$ uses fixed 20 $\mu$ W; self-heated $I_{on,n}$ includes metal resistance at $V_{GS}=V_{DS}=0.7$ V.

Fig. 3: DC inverter response without metal resistance at $V_{DD}=0.7$ V. (a) Voltage transfer characteristics, (b) DC power and (c) peak lattice temperature for baseline interconnects. Colors denote gate length; solid curves include self-heating, dashed curves are isothermal at 300 K. (d) Selected 12-nm device sections at $y=0$ under two static biases, with a common temperature scale and emphasized channels.

Structure	$\Delta T_{\max}$ (K)	Reduction (K)
Baseline	141.63	0.00
Redistributed interconnect	140.75	0.88
Substrate-directed path	140.83	0.80
Combined	139.96	1.67

TABLE I: Thermal performance of design stages on a common mesh

Model / effort label	$e_{T}$ (K)	$e_{C}$ (pp)	Status
GPT-6 / Light a	0 (ref.)	0 (ref.)	Reference
GPT-6 Astra / Ultra b	1.34e-12	3.20e-13	Pass
Claude Fable 5.1 / high	4.26e-13	2.42e-13	Pass
Claude Opus 5 / high (A)	4.98e-10	2.88e-10	Pass
Claude Opus 5 (B)	4.26e-13	2.42e-13	Pass
GPT-5.6 Sol / max	4.98e-10	2.88e-10	Pass

TABLE II: Cross-agent reproduction of the fixed thermal reference cases

Parameter	GPT study	Claude baseline $\to$ C4
Sheets per tier (total)	4 (8)	1 (2)
$L_{g},L_{h},W$ (nm)	12, 16, 40	20, 30, 50
$t_{n},t_{p}$ (nm)	0.65, 0.70	0.65, 0.65
Gate dielectric (nm)	1	3 (HfO 2 )
Within-tier gap (nm)	6	Not applicable
Inter-tier gap (nm)	20	26

TABLE III: Device parameters for the two design studies

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Mar 31, 2026J/K move · Enter open · S save

From Physics to Surrogate Intelligence: A Unified Electro-Thermo-Optimization Framework for TSV Networks

Mohamed Gharib, Leonid Popryho, Inna Partin-Vaisband

Department of Electrical and Computer Engineering, University of Illinois Chicago, Chicago, IL 60607, USA

Electronic Design Automation Surrogate Modeling Physics-Informed GNNs

Open paper AskPDF arXiv

High-density through-substrate vias (TSVs) enable 2.5D/3D heterogeneous integration but introduce significant signal-integrity and thermal-reliability challenges due to electrical coupling, insertion loss, and self-heating. Conventional full-wave finite-element method (FEM) simulations provide high accuracy but become computationally prohibitive for large design-space exploration. This work presents a scalable electro--thermal modeling and optimization framework that combines physics-informed analytical modeling, graph neural network (GNN) surrogates, and full-wave sign-off validation. A multi-conductor analytical model computes broadband S-parameters and effective anisotropic thermal conductivities of TSV arrays, achieving

5\%

10\%

relative Frobenius error (RFE) across array sizes up to

15\times15

. A physics-informed GNN surrogate (TSV-PhGNN), trained on analytical data and fine-tuned with HFSS simulations, generalizes to larger arrays with mean RFE below

5\%

in-distribution. The surrogate is integrated into a multi-objective Pareto optimization framework targeting reflection coefficient, insertion loss, worst-case crosstalk (NEXT/FEXT), and effective thermal conductivity. Millions of TSV configurations can be explored within minutes, enabling exhaustive layout and geometric optimization that would be infeasible using FEM alone. Final designs are validated with Ansys HFSS and Mechanical, showing strong agreement. The proposed framework enables rapid electro--thermal co-design of TSV arrays while reducing per-design evaluation time by more than six orders of magnitude.

Abstract

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