Hardware-Software Co-Design

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1 paper in the last four weeks, down 75% on the four weeks before. 0.0% of all new papers.

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Latest papers 46

May 7, 2026cs.AR

LLM-Driven Design Space Exploration of FPGA-based Accelerators

Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.

Vinamra Sharma, Xingjian Fu, Jude Haris +1

School of Computing Science, University of Glasgow, Scotland, UK

Large Language Model-Guided Optimization Electronic Design Automation Hardware-Software Co-Design FPGA-Based Neural Network Acceleration

May 6, 2026cs.LG

TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators

Reducing power consumption in AI accelerators is increasingly important. Approximate computing can reduce power consumption while keeping the accuracy loss small. Since multipliers are power-hungry components in AI models, this paper focuses on synthesizing low-power approximate multipliers (AxMs). Unlike prior works that design AxMs separately from AI model training, we present TRAM, which jointly optimizes the AxM structure and AI model parameters to lower power with small accuracy loss. Experiments show that compared to state-of-the-art AxMs, TRAM achieves up to 25.05% AxM power reduction on CNNs with CIFAR-10, and reduces power by up to 27.09% on vision transformers with ImageNet.

Chang Meng, Hanyu Wang, Yuyang Ye +3

Eindhoven University of Technology Eindhoven, The Netherlands · University of California, Los Angeles Los Angeles, USA · Chinese University of Hong Kong Hong Kong, China +2

AI Accelerator Inference Energy-Efficient ML Hardware-Software Co-Design Approximation Algorithms Approximate Computing

May 3, 2026cs.AR

ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA

Vision Mamba (ViM) models offer a compelling efficiency advantage over Transformers by leveraging the linear complexity of State Space Models (SSMs), yet efficiently deploying them on FPGAs remains challenging. Linear layers struggle with dynamic activation outliers that render static quantization ineffective, while uniform quantization fails to capture the weight distribution at low bit-widths. Furthermore, while associative scan accelerates SSMs on GPUs, its memory access patterns are misaligned with the streaming dataflow required by FPGAs. To address these challenges, we present ViM-Q, a scalable algorithm-hardware co-design for end-to-end ViM inference on the edge. We introduce a hardware-aware quantization scheme combining dynamic per-token activation quantization and per-channel smoothing to mitigate outliers, alongside a custom 4-bit per-block Additive Power-of-Two (APoT) weight quantization. The models are deployed on a runtime-parameterizable FPGA accelerator featuring a linear engine employing a Lookup-Table (LUT) unit to replace multiplications with shift-add operations, and a fine-grained pipelined SSM engine that parallelizes the state dimension while preserving sequential recurrence. Crucially, the hardware supports runtime configuration, adapting to diverse dimensions and input resolutions across the ViM family. Implemented on an AMD ZCU102 FPGA, ViM-Q achieves an average 4.96x speedup and 59.8x energy efficiency gain over a quantized NVIDIA RTX 3090 GPU baseline for low-batch inference on ViM-tiny. This co-design shows a viable path for deploying ViM models on resource-constrained edge devices.

Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung +2

City University of Hong Kong, Hong Kong

Efficient Neural Network Inference Edge Inference Activation Quantization Hardware-Software Co-Design FPGA-Based Neural Network Acceleration Neural Network Quantization

May 3, 2026cs.IT

SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation

Channel estimation is crucial in 5G communication networks for optimizing transmission parameters and ensuring reliable, high-speed communication. However, the use of multiple-input and multiple-output (MIMO) and millimeter-wave (mmWave) in 5G networks presents challenges in achieving accurate estimation under strict latency requirements on resource-limited hardware platforms. To address these challenges, we propose SwiftChannel, an algorithm-hardware co-design framework that integrates a hardware-friendly deep learning-based channel estimator with a dedicated accelerator. Our approach employs a convolutional neural network enhanced with a parameter-free attention mechanism, which effectively reconstructs full-resolution spatial-frequency domain channel matrices from low-resolution least squares (LS) estimates. We further develop a multi-stage model compression pipeline combining knowledge distillation, convolution re-parameterization, and quantization-aware training, resulting in substantial model size reduction with negligible accuracy loss. The hardware accelerator, implementing the compressed model and the LS estimator on FPGA platforms using High-level Synthesis (HLS), features a fine-grained pipeline architecture and optimized dataflow strategies. Tested on a Zynq UltraScale+ RFSoC, the accelerator achieves sub-millisecond latency, providing up to 24x speed-up and over 33x improvement in energy efficiency compared to GPU-based solutions. Extensive evaluations demonstrate that the proposed design generalizes not only across various noise levels and user mobilities, but also to a variety of unseen channel profiles, outperforming state-of-the-art baselines. By unifying algorithmic innovation with hardware-aware design, our work presents a future-proof channel estimation solution for 5G MIMO systems.

Shengzhe Lyu, Yuhan She, Di Duan +5

Department of Computer Science, City University of Hong Kong, Hong Kong · Department of Electrical Engineering, City University of Hong Kong, Hong Kong · Department of Information Engineering, The Chinese University of Hong Kong, Hong Kong +2

Wireless Communications Hardware-Software Co-Design Channel Estimation FPGA-Based Neural Network Acceleration

Apr 28, 2026cs.NI

Assistants, Not Architects: The Role of LLMs in Networked Systems Design

Designing the architecture of modern networked systems requires navigating a large, combinatorial space of hardware, systems, and configuration choices with complex cross-layer interactions. Architects must balance competing objectives such as performance, cost, and deployability while satisfying compatibility and resource constraints, often relying on scattered rules-of-thumb drawn from benchmarks, papers, documentation, and expert experience. This raises a natural question: can large language models (LLMs) reliably perform this kind of architectural reasoning? We find that they cannot. While LLMs produce plausible configurations, they frequently miss critical constraints, encode incorrect assumptions, and exhibit

stickiness'' to familiar patterns. A natural workaround--iterative validation via simulation or experimentation--is often prohibitively expensive at scale and, in many cases, infeasible, particularly when comparing hardware-dependent alternatives. Motivated by this gap, we present Kepler, a lightweight reasoning framework for architecture design that combines structured, expert-driven specifications with SMT-based optimization. Kepler encodes architecturally significant properties--requirements, incompatibilities, and qualitative trade-offs--about systems, hardware, and workloads as constraints, and synthesizes feasible designs that optimize user-defined objectives. It operates at an abstract level, capturing

rules-of-thumb'' rather than detailed system behavior, enabling tractable reasoning while preserving key interactions, and provides explanations for its decisions. Through experiments and case studies, we show that Kepler uncovers interactions missed by LLMs and supports systematic, explainable design exploration.

Pratyush Sahu, Rahul Bothra, Venkat Arun +3

Georgia Tech · UIUC · UT Austin +1

Satisfiability Modulo Theories Hardware-Software Co-Design LLM Reasoning

Apr 28, 2026cs.CV

DenseScout: Algorithm-System Co-design for Budgeted Tiny Object Selection on Edge Platforms

Deploying tiny object perception on edge platforms is challenging because practical systems must satisfy both strict compute budgets and end-to-end latency constraints. A common strategy is to first select a small number of candidate patches from a high-resolution image and then apply downstream processing only to the selected regions. However, existing detector-based frontends are not well aligned with this setting: strong offline detection accuracy does not necessarily yield effective low-budget patch prioritization, nor does it guarantee usable performance once transport and inference delays are considered. In this work, we study budgeted tiny object selection on edge platforms from a joint algorithm--system perspective. We present DenseScout, a lightweight dense-response selector with only 1.01M parameters, which directly ranks candidate patch locations from a high-resolution scene via a lightweight proxy input and is better aligned with low-budget tiny-object prioritization than detector-style frontends. To bridge offline selector quality and deployable utility, we further develop a transport-aware runtime realization on heterogeneous edge devices and adopt QoS-constrained recall, which counts a target as successfully perceived only if it is covered by the selected regions and the end-to-end processing finishes before the deadline. Experiments show that DenseScout consistently outperforms detector-based baselines in offline budgeted patch-selection evaluation, especially in low-budget regimes, while cross-platform results on RK3588 and Jetson Orin NX show that deployable performance depends jointly on selector quality and runtime realization efficiency. These results suggest that edge tiny object perception should be optimized as an algorithm--system co-design problem rather than as isolated model selection.

Xiong Zhouzhi, Zimo Zeng, Yi Chen +3

College of Electrical Engineering, Zhejiang University, Hangzhou, China

Small Object Detection Edge Inference Edge Computing Hardware-Software Co-Design

Apr 23, 2026cs.LG

Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models

This work presents a multi-layered methodology for efficiently accelerating multimodal foundation models (MFMs). It combines hardware and software co-design of transformer blocks with an optimization pipeline that reduces computational and memory requirements. During model development, it employs performance enhancements through fine-tuning for domain-specific adaptation. Our methodology further incorporates hardware and software techniques for optimizing MFMs. Specifically, it employs MFM compression using hierarchy-aware mixed-precision quantization and structural pruning for transformer blocks and MLP channels. It also optimizes operations through speculative decoding, model cascading that routes queries through a small-to-large cascade and uses lightweight self-tests to determine when to escalate to larger models, as well as co-optimization of sequence length, visual resolution & stride, and graph-level operator fusion. To efficiently execute the model, the processing dataflow is optimized based on the underlying hardware architecture together with memory-efficient attention to meet on-chip bandwidth and latency budgets. To support this, a specialized hardware accelerator for the transformer workloads is employed, which can be developed through expert design or an LLM-aided design approach. We demonstrate the effectiveness of the proposed methodology on medical-MFMs and on code generation tasks, and conclude with extensions toward energy-efficient spiking-MFMs.

Muhammad Shafique, Abdul Basit, Muhammad Abdullah Hanif +3

eBRAIN Lab, New York University (NYU) Abu Dhabi, Abu Dhabi, United Arab Emirates

Model Compression Efficient Multimodal Inference Hardware-Software Co-Design Multimodal Foundation Models Multimodal Learning

Apr 20, 2026cs.LG

M100: An Orchestrated Dataflow Architecture Powering General AI Computing

As deep learning-based AI technologies gain momentum, the demand for general-purpose AI computing architectures continues to grow. While GPGPU-based architectures offer versatility for diverse AI workloads, they often fall short in efficiency and cost-effectiveness. Various Domain-Specific Architectures (DSAs) excel at particular AI tasks but struggle to extend across broader applications or adapt to the rapidly evolving AI landscape. M100 is Li Auto's response: a performant, cost-effective architecture for AI inference in Autonomous Driving (AD), Large Language Models (LLMs), and intelligent human interactions, domains crucial to today's most competitive automobile platforms. M100 employs a dataflow parallel architecture, where compiler-architecture co-design orchestrates not only computation but, more critically, data movement across time and space. Leveraging dataflow computing efficiency, our hardware-software co-design improves system performance while reducing hardware complexity and cost. M100 largely eliminates caching: tensor computations are driven by compiler- and runtime-managed data streams flowing between computing elements and on/off-chip memories, yielding greater efficiency and scalability than cache-based systems. Another key principle was selecting the right operational granularity for scheduling, issuing, and execution across compiler, firmware, and hardware. Recognizing commonalities in AI workloads, we chose the tensor as the fundamental data element. M100 demonstrates general AI computing capability across diverse inference applications, including UniAD (for AD) and LLaMA (for LLMs). Benchmarks show M100 outperforms GPGPU architectures in AD applications with higher utilization, representing a promising direction for future general AI computing.

Yan Xie, Changkui Mao, Changsong Wu +34

Li Auto

AI Accelerator Inference LLM Inference Acceleration Hardware-Software Co-Design

Apr 13, 2026cs.RO

Identifying and Exploiting Structure in Robot Co-Design

Co-design is a high-dimensional search problem in the robot morphology and control design space. Efficient search requires exploiting the structure shaped by their interaction. To understand this structure, we analyze the landscapes of soft locomotion and manipulation tasks. We identify three patterns consistent across regions of their co-design spaces: 1) Within a region, quality varies along a low-dimensional manifold, with minimal variation orthogonal to it, reducing the effective search space dimensionality. 2) In higher-quality regions, the variance in quality is spread across more dimensions, necessitating search to expand dimensionality as quality improves. 3) In higher-quality regions, quality varies along joint morphology-control dimensions, requiring search along them. Using these insights, we devise an efficient co-design algorithm that yields 36% better co-designs than state-of-the-art baselines. We examine their exploration patterns and show that these baselines required an order of magnitude more function evaluations to find co-designs of comparable quality. Finally, we ablate our algorithm to verify that exploiting the identified structure was the key to efficient co-design.

Apoorv Vaish, Oliver Brock

Robotics and Biology Laboratory, Technische Universität Berlin · Science of Intelligence (SCIoI), Cluster of Excellence, Berlin · Robotics Institute Germany (RIG)

Robot Morphology-Control Co-Design Robotic Manipulation Robot Locomotion Hardware-Software Co-Design

Apr 10, 2026cs.RO

CableTract: A Co-Designed Cable-Driven Field Robot for Low-Compaction, Off-Grid Capable Agriculture

Conventional field operations spend most of their energy moving the tractor body, not the implement. Yet feasibility studies for novel agricultural vehicles rarely tie mechanics, energy harvest, draft, field geometry, economics, life-cycle CO2, and uncertainty quantification together on a single reproducible code path. This paper builds such a framework and applies it to CableTract, a two-module cable-driven field robot. A stationary Main Unit (winch + motor + battery + harvester module) (MU) and a lighter Anchor module (held by helical screw piles) tension a cable across a strip while a lightweight implement carriage rolls along it. The heavy bodies stay on the headland; only the carriage enters the field. The carriage runs a 10-implement library co-designed for the cable architecture. This co-design is the paper's central analytical lever. The framework is prototype-free. It chains a catenary cable model, a drivetrain efficiency chain, a stochastic draft model fitted to the co-designed library, an hourly solar + wind + battery simulator on six sites, a polygon coverage planner on a 50-field corpus, a contact-pressure compaction model, a discounted cash-flow economics engine with battery replacement and life-cycle CO2, and a global sensitivity analysis on 20 inputs. An operating-envelope sweep and an architectural-variant comparison close the loop. The full implementation is open source. Applied to the codesigned reference, the framework yields energy, compaction advantages and potential off-grid operation.

Ozgur Yilmaz

Adana Science and Technology University, Adana, Türkiye

Robotics Hardware-Software Co-Design Agricultural Robotics

Apr 7, 2026cs.RO

A Co-Design Framework for High-Performance Jumping of a Five-Bar Monoped with Actuator Optimization

The performance of legged robots depends strongly on both mechanical design and control, motivating co-design approaches that jointly optimize these parameters. However, most existing co-design studies focus on link dimensions and transmission ratios while neglecting detailed actuator design, particularly motor and gearbox parameter optimization, and are largely limited to serial open-chain mechanisms. In this work, we present a co-design framework for a planar closed-chain five-bar monoped that jointly optimizes mechanical design, motor and gearbox parameters, and control parameters for dynamic jumping. The objective is to maximize jump distance while minimizing mechanical energy consumption. The framework employs a two-stage optimization approach, where actuator optimization generates a mapping from gear ratio to actuator mass, efficiency, and peak torque, which is then incorporated into CMA-ES-based co-design optimization of the robot design and control parameters. Simulation results demonstrate an improvement of approximately 30.4% in jump distance and an 11.5% reduction in mechanical energy consumption compared to a nominal design, highlighting the effectiveness of the proposed framework for high-performance and energy-efficient planar jumping.

Aastha Mishra, Aman Singh, Shishir Kolathaya

Department of Cyber-Physical Systems (CPS), Indian Institute of Science (IISc), Bengaluru, India.

Legged Robotics Mechanism Design Hardware-Software Co-Design

Feb 28, 2026cs.MM

Amanous: Distribution-Switching for Superhuman Piano Density on Disklavier

A player piano can strike more keys, across more of the register, and faster than any pianist can reach. Three traditions dominate composition in that region, namely Nancarrow's tempo canons, Xenakis' stochastic distributions, and L-system grammars. They have developed in isolation, and none of them accounts for the instrument itself. A Disklavier does not answer instantly, because a loud note reaches the string sooner than a soft one, so music written as if the mechanism were transparent arrives distorted. We present Amanous, a hardware-aware composition system for the Yamaha Disklavier that unifies the three traditions through distribution-switching, in which each grammar symbol selects an entire distributional regime rather than adjusting parameters within a fixed one. A four-layer pipeline carries a symbol from grammar to actuation-ready MIDI. An L-system fixes the macro-form, each symbol is mapped to distributions and a tempo-canon ratio, events are sampled and time-scaled, and a hardware layer pre-compensates velocity-dependent latency and enforces the key-reset time. Convergence points close a feedback loop, letting the music's own temporal structure trigger the next switch. Sections from different symbols remain statistically separable at the output, and ablating the L-system, the tempo canon, or the hardware compensation each degrades a distinct property. Under the modelled latency curve, pre-compensation takes the mean onset error from roughly 18 ms to below the instrument's 1 ms scanning resolution. Structured and random textures are most separable near 25 notes/s, and melodic metrics lose their discriminative power over the 40-100 notes/s band, above which the difference is consistent with distributional content rather than melodic order. All results are computational, nothing was played or measured on an instrument, and a psychoacoustic protocol is proposed for future work.

Joonhyung Bae

Graduate School of Culture Technology KAIST (Korea Advanced Institute of Science and Technology) Daejeon, South Korea

Symbolic Music Generation Hardware-Software Co-Design Music Generation

Apr 20, 2025cs.RO

Soft yet Effective Robots via Holistic Co-Design

Soft robots promise inherent safety via their material compliance for seamless interactions with humans or delicate environments. Despite progress, the field struggles to balance task-specific performance with broader factors like durability and manufacturability--a difficulty that we find is compounded by traditional sequential design processes with their lack of feedback loops. In this perspective, we review emerging co-design approaches that simultaneously optimize the soft robot's body and brain, enabling the discovery of unconventional designs highly tailored to the given tasks. Their adoption is limited by narrow objectives, gaps between simulated and real performance, and computational cost. To address these challenges, we propose a holistic co-design framework that incorporates a broader range of design values, integrates real-world prototyping to refine evaluations, and boosts efficiency through surrogate metrics and model-based control strategies. Finally, we outline research priorities in design priors and metrics, AI-assisted evaluation, and balancing computational refinement with physical testing and safety with performance.

Maximilian Stölzle, Niccolò Pagliarani, Francesco Stella +6

Laboratory for Information & Decision Systems, Massachusetts Institute of Technology, Cambridge, 02139, MA, USA. · Cognitive Robotics, Delft University of Technology, Mekelweg 2, Delft, 2628 CD, Netherlands. · Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, 02139, MA, USA. +4

Hardware-Software Co-Design Soft Robotics

Oct 29, 2024cs.NI

Accelerating Stateful Network Applications with Performance Prediction on SoC SmartNICs

Offloading stateful network functions to multi-threaded SoC SmartNICs promises significant performance and cost benefits. However, realizing this potential is hindered by two fundamental challenges. First, without performance guidance, developers are forced into a slow, manual trial-and-error cycle of deploying and testing to find a feasible resource allocation. Second, sustaining performance under changing traffic requires adapting state residency and handling overload within memory layouts fixed at compile time. This paper introduces Vela, a framework that addresses both challenges through a model-driven, compile-time/runtime co-design. Its core is a predictive compiler that replaces the manual tuning loop with fast, automated analysis, using a novel, state-centric analytical model to estimate the throughput ceiling of any given resource allocation plan. This is complemented by a lightweight runtime that dynamically manages cache contents within the compiled memory layout and mitigates overload. We implement and evaluate Vela on Netronome Agilio and NVIDIA BlueField 3 SmartNICs across four NFs. Vela reduces host CPU or on-board Arm core usage by 62.9%-91.9% relative to the best baseline achieving the same throughput. For the NATLB workload, vela also improves throughput by 15.2%-120.8% over the best baseline at the same host/Arm core count.

Shaoke Xi, Jiaqi Gao, Fuliang Li +2

Alibaba Cloud · Northeastern University, China · Harvard University

Hardware-Software Co-Design

Jun 14, 2017cs.RO

Context-Aware System Synthesis, Task Assignment, and Routing

The design and organization of complex robotic systems traditionally requires laborious trial-and-error processes to ensure both hardware and software components are correctly connected with the resources necessary for computation. This paper presents a novel generalization of the quadratic assignment and routing problem, introducing formalisms for selecting components and interconnections to synthesize a complete system capable of providing some user-defined functionality. By introducing mission context, functional requirements, and modularity directly into the assignment problem, we derive a solution where components are automatically selected and then organized into an optimal hardware and software interconnection structure, all while respecting restrictions on component viability and required functionality. The ability to generate complete functional systems directly from individual components reduces manual design effort by allowing for a guided exploration of the design space. Additionally, our formulation increases resiliency by quantifying resource margins and enabling adaptation of system structure in response to changing environments, hardware or software failure. The proposed formulation is cast as an integer linear program which is provably

\mathcal{NP}

-hard. Two case studies are developed and analyzed to highlight the expressiveness and complexity of problems that can be addressed by this approach: the first explores the iterative development of a ground-based search-and-rescue robot in a variety of mission contexts, while the second explores the large-scale, complex design of a humanoid disaster robot for the DARPA Robotics Challenge. Numerical simulations quantify real world performance and demonstrate tractable time complexity for the scale of problems encountered in many modern robotic systems.

Jason Ziglar, Ryan Williams, Alfred Wicks

Combinatorial Optimization Robotics Hardware-Software Co-Design Integer Linear Programming

Date pendingcs.MS

FP8 is All You Need (Part 2): Full-FP64 3-D FFT on FP8-Generation Tensor CoresThe Integer-Epilogue Wall and the Minimal Hardware That Would Remove It

The NVIDIA Blackwell Ultra (B300) GPU cuts FP64 vector throughput

\sim 30\times

while multiplying FP8 tensor throughput. After the recovery of FP64 GEMM via Ozaki Scheme II on FP8 tensor cores and the Tensor-Memory Equilibrium model of the companions ("FP8 is All You Need, Part 1" and "Ozaki 2.5") we ask whether the fifth canonical HPC primitive, the full-FP64

1024^3

3-D FFT, can be carried by the same substrate, and answer with a design and its limit. It is a Bailey six-step transform with no FP64 arithmetic: FP8-tensor DFT GEMMs with fused twiddles, residue-domain Karatsuba combines and exact CRT reconstruction whose bulk is a small GEMM on the FP16 tensor path and whose remainder is a Kulisch fixed-point accumulation with a two-sided modulo-

M

lift, so the only rounding is the final conversion; constants are machine-generated and verified bit-exactly. The central finding: the binding resource is not floating point but a per-output integer epilogue with floor

(c_{\rm epi}/8),B_{\rm mem}

,

c_{\rm epi} \approx 203

-

281

instructions per output: on B300 it holds the transform at 63-87 ms against a 12.9 ms roof (

4.9

-

6.7\times

short); at most

1.3

-

1.9\times

faster than the collapsed native path, possibly no faster at realised issue rates; no software route reaches the roof; on the NVIDIA Rubin GPU emulation loses

8

-

11\times

. An FP32 variant meets the same wall: the cause is per-scalar reconstruction, not FP64. Each floor term names its remedy: the NVIDIA B200 GPU's INT8 tensor core restored with a position-weighted cross-column accumulation primitive, a load-path deconstruction datapath shared with the companions, two ISA idioms and modular reduction at the MMA output give 16.0-23.5 ms with minor hardware and 12.9-15.0 ms with one moderate ask. All figures are projected floors, not measurements, with sensitivities and the FP8 layout condition given.

Satoshi Matsuoka

Director, RIKEN Center for Computational Science (R-CCS), Kobe, Hyogo, Japan

GPU Kernel Optimization GPU Acceleration High-Performance Computing Hardware-Software Co-Design