RTL Code Generation

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HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation
Aug 7, 2026Tairan Cheng, Yi Liu, Dongsheng Zuo +6Electronic Design Automation LLM-Based Program Synthesis
The Chinese University of Hong Kong Hong Kong, China · Southeast University Nanjing, China
LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
Aug 3, 2026Pingqing Zheng, Jiayin Qin, Fuqi Zhang +5LLM-Based Program Synthesis RTL Code Generation
University of Minnesota, Twin Cities, Minneapolis, Minnesota, USA · Columbia University, New York City, New York, USA · Northwestern University, Evanston, Illinois, USA
VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space
Aug 3, 2026Yu-Tung Liu, Cunxi YuLLM Agent Verification RTL Code Generation
University of Maryland, College Park College Park, USA
RTLCurator: Label-Efficient Data Curation for RTL Generation
Jul 31, 2026Siyang Cai, Cangyuan Li, Wenjing Chang +4Training Data Curation Training Data Selection
School of Advanced Interdisciplinary Sciences, University of Chinese Academy of Sciences, Beijing, China · CICS, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China · Computer Network Information Center, Chinese Academy of Sciences, Beijing, China +1
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
Jun 16, 2026You Li, Samuel Mandell, David Z. PanCode Generation LLM-Based Program Synthesis
The University of Texas at Austin · USA
LLM4RTL: Tool-Assisted LLM for RTL Generation
Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1Code Generation RTL Code Generation
UC Riverside · Riverside, CA, USA · Futurewei +1
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Jun 9, 2026Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali +6LLM Fine-Tuning Electronic Design Automation
University of Illinois Urbana-Champaign
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
Jun 8, 2026Jing Wang, Shang Liu, Wenji Fang +3LLM Evaluation Benchmark Design
Hong Kong University of Science and Technology
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Code Generation LLM-Based Program Synthesis
Department of Electrical and Computer Engineering (ECE), University of Central Florida, Orlando, FL 32816, USA
Alpha-RTL: Test-Time Training for RTL Hardware Optimization
Jun 3, 2026Peilong Zhou, Zhirong Chen, Cangyuan Li +4RL for Language Models Test-Time Optimization
1SKLP, Institute of Computing Technology, Chinese Academy of Sciences · University of the Chinese Academy of Sciences · School of Advanced Interdisciplinary Sciences
StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
Jun 2, 2026Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2RL for Code Generation Process Reward Models
IBM Research San Jose, CA, USA
EstRTL: Functional Estimation Guided RTL Code Generation
Jun 1, 2026Qi Xiong, Renzhi Chen, Bowei Wang +3Code Generation Agentic Code Generation
College of Computer Science and Technology, National University of Defense Technology, Changsha, China · Defense Innovation Institute, Academy of Military Science (AMS), Beijing, China · School of Computer Science and Technology, Shandong University, Qingdao, China +2
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
May 26, 2026Zehua Pei, Hui-Ling Zhen, Yu Zhang +3Large Language Model-Guided Optimization Execution-Guided Code Generation
The Chinese University of Hong Kong · Huawei Technologies Co., Ltd
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
May 15, 2026Jing Wang, Shang Liu, Hangan Zhou +1LLM Evaluation Electronic Design Automation
Hong Kong University of Science and Technology · Clear Water Bay, Hong Kong
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
May 13, 2026Zhongkai Yu, Yichen Lin, Chenyang Zhou +12RL for Code Generation Code Generation
UCSD · Columbia University
From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation
Apr 30, 2026Guang Yang, Xing Hu, Xiang Chen +1Multimodal Grounding Code Generation
State Key Laboratory of Blockchain and Data Security, Zhejiang University, Hangzhou, China · Hangzhou High-Tech Zone (Binjiang) Institute of Blockchain and Data Security, Hangzhou, China · School of Artificial Intelligence and Computer Science, Nantong University, Nantong, China
How LLMs Fail and Generalize in RTL Coding for Hardware Design?
Apr 26, 2026Guan-Ting Liu, Chao-Han Huck Yang, Chenhui Deng +3LLM Evaluation Code Generation
NVIDIA Research
LEGO: An LLM Skill-Based Front-End Design Generation Platform
Apr 25, 2026Jincheng Lou, Ruohan Xu, Jiecheng Ma +3Electronic Design Automation Code Generation
School of IC, Peking University · School of EECS, Peking University · School of Microelectronics, Xidian University +2
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
Apr 21, 2026Cagri EryilmazElectronic Design Automation Code Generation
ChipCraftX San Francisco, CA
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
Apr 18, 2026Minghao Shao, Zeng Wang, Weimin Fu +5LLM Evaluation Language Model Generation Evaluation
NYU Tandon School of Engineering, USA · Kansas State University, USA · NYU Abu Dhabi, UAE
COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation
Apr 16, 2026Heng Ping, Peiyu Zhang, Shixuan Li +5Multi-Objective Evolutionary Optimization Code Generation
University of Southern California United States
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design
Nov 6, 2023James T. MeechElectronic Design Automation RTL Code Generation
University of Cambridge

Aug 7, 2026, cs.ARJ/K move · Enter open · S save

HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

Tairan Cheng, Yi Liu, Dongsheng Zuo, Zhengyuan Shi+5

The Chinese University of Hong Kong Hong Kong, China · Southeast University Nanjing, China

Electronic Design Automation LLM-Based Program Synthesis RTL Code Generation

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Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing and debugging low-level code. We present HINT, an executable hardware-intent intermediate representation layer between behavioral specifications or executable oracles and RTL. HINT makes RTL-relevant microarchitecture explicit, supports pre-RTL checking, and supplies explicit RTL-lowering obligations. We evaluate HINT using both a minimal single-agent flow and a full staged workflow. Across seven operator cases, the HINT-mediated route, with no post-synthesis QoR refinement, produces contract-compliant synthesizable RTL on 7/7 cases; Direct C2RTL and C2HLSC apply to five cases and succeed on 5/5 and 1/5, respectively. Under matched Design Compiler synthesis, HINT reduces area by 5.0%--26.2% relative to five manual RTL implementations and by 8.9%--86.1% relative to five accepted Direct C2RTL results. RealBench AES and SDC, together with a Vortex VPU synthesizing to 561.67k~

μ\mathrm{m}^2

, further demonstrate specification-driven, protocol-rich, memory-rich, and hierarchical designs. In the controlled operator study, the HINT-mediated route shows better observed convergence and avoids the severe implementation-quality degradation seen in several direct-generation results.

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