Fault tolerance estimation in digital circuits with visualised generative networks

In bearing vibration datasets, most samples receive predicted fault probabilities close to 0 or 1, while samples with intermediate (gray-zone) probabilities are rare. Such borderline samples are important because they reflect conditions in which maintenance decisions may require additional inspection or a conservative response and are useful for studying decision boundaries. To address this scarcity, this paper proposes and compares two approaches that generate vibration signals whose predicted fault probability matches a target probability of 0.25, 0.50, or 0.75. We use the average output of a heterogeneous ensemble classifier with different architectures and random initializations as a fixed, gradient-accessible probability oracle. The first, training-based approach, Probability-Regularized Generative Adversarial Network (PR-GAN), extends Wasserstein Generative Adversarial Network with Gradient Penalty (WGAN-GP) and edits a real signal through a residual generator while pushing the classifier output toward the target probability. The second is a training-free, per-sample Wachter-style counterfactual (CF) procedure that directly optimizes each input signal to reach the target probability while remaining close to the source signal. We evaluate both methods on the Case Western Reserve University (CWRU) and Paderborn bearing datasets using mean absolute target-probability error, time-domain total variation, and frequency-domain log power spectral density (log-PSD) differences. Across all settings, CF reaches the target with a mean absolute probability error of 0.005-0.008 and a within-tolerance success rate of 1.000 on retained samples, whereas PR-GAN's mean error is 0.046-0.059 with success rates between 0.501 and 0.680. CF therefore steers the probability more reliably and requires smaller average L1 changes, whereas PR-GAN has a lower reported runtime in most settings.

Accurate routability estimation during physical design is important for reducing costly post-routing iterations. Prior learning-based methods treat this task as deterministic prediction, mapping placement-stage features to a single congestion or DRC outcome. We instead formulate routability estimation as a conditional generation problem, where both routing congestion and DRC violations are modeled as spatially structured routability fields. Our framework, Conditional Latent Diffusion for Routeability estimation (CLDRoute), uses physics-aware conditioning and task-specific latent modeling to handle the different characteristics of congestion and DRC maps. This allows our method to supports sample-based inference, producing both a mean prediction and a spatial uncertainty estimate for the same input design. On CircuitNet 2.0 (N28), our method achieves, for DRC violation generation, an SSIM of 0.9678, an MAE of 0.0028, and a TopK@1% of 0.3494; for congestion generation, it achieves an SSIM of 0.9031, an MAE of 0.0286, and an NZ-Pearson of 0.3692. Overall, our framework provides a more practical view of routability at placement by generating both the expected outcome and its uncertainty.

EDA problems are graph-structured, but not all graph-structured problems call for the same GNN computation. We argue that successful GNN-for-EDA methods are those whose propagation, aggregation, and supervision align with the native algebra of the target task. Concretely: static timing analysis is a max-plus/min-plus recurrence on a topologically ordered DAG, structurally aligned with asynchronous DAG-GNNs; placement is governed by hypergraph wirelength and density penalties and is exploited by differentiable placers rather than by message-passing GNNs alone; routing congestion is a sparse demand-supply field over a layout grid; switching-activity propagation is a probabilistic recurrence on a directed netlist; IR drop is a linear system on the power-delivery network; and analog symmetry extraction is a discrete constraint-prediction problem on schematic graphs. Through these task-by-task alignments we (i) review the GNN architectural toolkit relevant to circuits, (ii) formalize how circuit graphs differ from generic graphs (directed, heterogeneous, multi-scale, with sequential and clock structure), (iii) characterize where current methods succeed and where the algebra-architecture mismatch limits them, and (iv) identify failure modes--stage leakage, proxy-to-signoff gap, calibration, and design-distribution shift--that we believe are likely to dominate the next phase of work. We position the paper as a GNN-for-EDA, task-aligned analysis rather than a comprehensive AI-for-chip-design survey. Continuous SE(3)-equivariant geometric GNNs are usually mismatched to Manhattan digital layout, and LLM-for-RTL, HLS, and RL/diffusion-based topology generation are outside our scope.