C2Flight: A Closed-Loop Co-Simulation Framework for Early-Stage Evaluation of Heterogeneous UAV Computing Systems
Abstract
Early-stage design of heterogeneous UAV computing systems requires evaluating how algorithm, hardware, communication, and system topology affect closed-loop flight before the complete system is available. However, design choices interact through the robotic feedback loop, making task performance difficult to predict from isolated component metrics, while existing execution-driven approaches postpone system-level design feedback until the computing system is integrated. This work presents C2Flight, a closed-loop co-simulation framework that represents target systems as parameterized dataflow graphs and integrates models of hardware under design with independently accessible physical hardware through a unified node interface. Its graph runtime captures the combined effects of buffering, activation, resource sharing, communication, and local timing on closed-loop flight behavior. Validation against onboard and wireless offboard physical computing pipelines confirms its timing fidelity and closed-loop prediction accuracy. Two case studies demonstrate early-stage exploration of deployment and accelerator bit-width choices. These results show that C2Flight exposes system-level design trade-offs before full-system integration, enabling rapid early-stage design refinement.
Figures & tables
| Group | Parameter | Representative choices |
| Data exchange | Port storage mode | Queued storage, latest-value storage, direct handoff |
| Full-buffer policy | Blocking, dropping new inputs, dropping oldest inputs | |
| Read policy | Data consumption, data retention | |
| Packet selection policy | FIFO order, latest arrival, latest source timestamp | |
| Connection mode | Direct transfer, broadcast, tagged routing | |
| Node activation | Trigger type | Data-driven, periodic, completion-triggered, external |
| Onboard | Offboard | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| Mean | Std. | Norm. (%) | Mean | Std. | Norm. (%) | ||||
| CH | 127.76 | 11.51 | 3.02 | 2.42 | CH | 415.50 | 34.33 | 7.82 | 1.88 |
| CM | 127.72 | 11.51 | 2.98 | 2.39 | CM | 415.87 | 34.28 | 7.61 | 1.83 |
| SM | 121.37 | 0.01 | 10.28 | 8.24 | SM | 226.05 | 18.99 | 165.21 | 42.22 |
| GT | 124.74 | 11.54 | – | – | GT | 416.86 | 35.89 | – | – |
| Onboard | |||||
|---|---|---|---|---|---|
| Speed (m/s) | GT | CH | CM | SC | SW |
| 0.80 | 7/7 | 7/7 | 7/7 | 7/7 | 7/7 |
| 0.90 | 7/7 | 7/7 | 6/7 | 7/7 | 7/7 |
| 1.00 | 2/7 | 1/7 | 0/7 | 7/7 | 7/7 |
| 1.10 | 1/7 | 0/7 | 0/7 | 5/7 | 7/7 |
| 1.20 | 0/7 | 0/7 | 0/7 | 0/7 | 0/7 |
| Config. | Position MAE (cm) | Integrated error (m s) |
|---|---|---|
| CH | 3.040 | 0.326 |
| CM | 3.782 | 0.406 |
| SC | 12.456 | 1.335 |
| SW | 14.661 | 1.570 |
| Speed cap | INT4 | INT8 | FP16 | FP32 |
|---|---|---|---|---|
| m/s | 5/5 | 5/5 | 5/5 | 5/5 |
| m/s | 5/5 | 5/5 | 4/5 | 2/5 |
| m/s | 0/5 | 5/5 | 0/5 | 0/5 |
| m/s | 0/5 | 0/5 | 0/5 | 0/5 |
Heterogeneous Computing
Heterogeneous computing studies how to coordinate different processors, accelerators, and memory systems to improve performance, efficiency, and cost.
See all 80 papers