High Level Synthesis

High-level synthesis (HLS) automates the translation of high-level code (like C++) into hardware designs, accelerating the development of hardware accelerators. Current research emphasizes using machine learning, particularly graph neural networks (GNNs) and large language models (LLMs), to optimize the HLS process, focusing on efficient design space exploration and accurate performance prediction before full synthesis. This improves the efficiency and productivity of hardware design, impacting fields like AI acceleration and embedded systems by enabling faster development cycles and potentially higher-performing hardware.

Papers

January 14, 2024

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo
Gene Level GNN Hardware Design Design Space Exploration High Level Synthesis

December 23, 2023

Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference
Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang
Full Potential LLM Inference Large Language Model Inference High Level Synthesis Inference Workload Spatial Accelerator

November 6, 2023

Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design
James T. Meech
Simulation Study Generate Quick High Level Synthesis Random Number Generator Integrated Circuit Design

September 27, 2023

GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis
Chenfeng Zhao, Zehao Dong, Yixin Chen, Xuan Zhang, Roger D. Chamberlain
Graph Neural Network High Level Synthesis GNN Framework GNN Inference Graph Neural Network Inference

August 15, 2023

SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR
Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
High Level Synthesis Modern Compiler Hardware Description Language Optimization Performance E Graph

May 18, 2023

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation
Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, Jason Cong
Field Programmable Gate Array Past Present Temporal Program High Level Synthesis Electronic Design Automation Cross Modal Representation Learning Hardware Description Language Domain Specific Accelerator

March 14, 2023

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators
Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjodin, Bjorn Lisper
New Framework Average Approximation Pareto Optimal DNN Accelerator Trade Offs High Level Synthesis

February 17, 2023

HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis
Zhigang Wei, Aman Arora, Ruihao Li, Lizy K. John
Open Source Field Programmable Gate Array High Level Synthesis Verilog Textbook

February 13, 2023

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science
Maksim Levental, Arham Khan, Ryan Chard, Kazutomo Yoshii, Kyle Chard, Ian Foster
Low Latency Experimental Study High Throughput High Level Synthesis Bragg Peak

January 3, 2023

Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture
CS Reddy, Krishna Anand
Multi Layer Good Thing High Level Synthesis

July 30, 2022

Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis
Soheil Nazar Shahsavani, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram
Area MaPPing Field Programmable Gate Array High Level Synthesis Boolean Function Logic Design Efficient Compilation Logical Neural Network

July 3, 2022

Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis
Mang Yu, Sitao Huang, Deming Chen
Field Programmable Gate Array Hardware Accelerator Hybrid Machine Learning High Level Synthesis

March 8, 2022

A Compilation Flow for the Generation of CNN Inference Accelerators on FPGAs
Seung-Hun Chung, Tarek S. Abdelrahman
Faithful Generation Field Programmable Gate Array High Level Synthesis Inference Accelerator CUDA Kernel OpenCL Code

January 18, 2022

High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao
Graph Neural Network Benchmark Platform Timing Analysis High Level Synthesis

November 29, 2021

A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration
Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi
Design Space Hardware Design High Level Synthesis Optimal Synthesis

November 17, 2021

Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks
Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong
Graph Neural Network Hardware Design Efficient Architecture High Level Synthesis FPGA Accelerator Control Flow

High Level Synthesis

Papers

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs

Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference

Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design

GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis

SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators

HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture

Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis

Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis

A Compilation Flow for the Generation of CNN Inference Accelerators on FPGAs

High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing

A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration

Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks