Verilog Textbook

Verilog textbooks and associated datasets are undergoing a transformation driven by the application of large language models (LLMs) to automate various aspects of hardware design. Current research focuses on using LLMs for tasks such as Verilog code generation, bug localization, and autocompletion, often employing fine-tuning strategies on large, curated datasets derived from open-source repositories and textbooks to improve model performance. This work aims to improve the efficiency and accuracy of hardware design and verification processes, potentially reducing development time and errors in the creation of complex digital systems.

Papers

October 30, 2024

The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang, Didier Chetelat, Dimitrios Tsaras, Yingxue Zhang, Hui-Ling Zhen, Jianye Hao, Mingxuan Yuan
Graph Drawing Quality Estimation Logic Synthesis Hardware Description Language Biological Circuit Digital Circuit Apprenticeship Learning Verilog Textbook

September 23, 2024

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
Large Language Model Location Information Verilog Code Generation Functional Verilog Description BUG Localization Verilog Textbook

July 2, 2024

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation
Yongan Zhang, Zhongzhi Yu, Yonggan Fu, Cheng Wan, Yingyan Celine Lin
Data Set Functional Verilog Description Verilog Textbook

October 16, 2023

Towards the Imagenets of ML4EDA
Animesh Basak Chowdhury, Shailja Thakur, Hammond Pearce, Ramesh Karri, Siddharth Garg
Supervised ImageNet Logic Synthesis Verilog Code Generation Hardware Platform Verilog Textbook

July 28, 2023

VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, Siddharth Garg
Large Language Model Verilog Code Generation Design Automation Verilog Textbook

April 26, 2023

A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Enrique Dehaerne, Bappaditya Dey, Sandip Halder, Stefan De Gendt
Product Design Deep Learning Framework Hardware Description Language Verilog Code Generation Functional Verilog Description Verilog Textbook

February 17, 2023

HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis
Zhigang Wei, Aman Arora, Ruihao Li, Lizy K. John
Open Source Field Programmable Gate Array High Level Synthesis Verilog Textbook

December 13, 2022

Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg
Verilog Code Generation Functional Verilog Description Verilog Textbook

Verilog Textbook

Papers

The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation

Towards the Imagenets of ML4EDA

VeriGen: A Large Language Model for Verilog Code Generation

A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis

Benchmarking Large Language Models for Automated Verilog RTL Code Generation