Chip Design

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3 papers in the last 28 days · 0.0% of indexed attention

Twelve weeks of publication activity for this topic as it is defined today.

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Period ending 2026-09-21

1 new paper

A weekly snapshot of new work published in Chip Design.

Period ending 2026-09-07

2 new papers

A weekly snapshot of new work published in Chip Design.

38 papers

Latest in Chip Design

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  1. From Ideas to Actions: A Public-Data Decision-Support Toolchain Across the Venture Lifecycle

    Sep 14, 2026Lei QuFinancial Strategy ResearchDecision Support

  2. Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs

    Sep 3, 2026Yujie Zhang, Huiying Lan, Ehsan Aghapour +5Sparse Deep Neural Network AcceleratorsParallel

  3. RACE-AIMC: Selective Inference for Heterogeneous Analog In-Memory Accelerators at the Edge

    Sep 2, 2026Osama Yousuf, Martin Lueker-BodenIn-Memory ComputingAccelerator

  4. ICM Out! Better Tournament Strategy from Computed Continuations, vs. Solvers and LLMs

    Aug 10, 2026Boning Li, Longbo HuangImperfect-Information GamesGame Theory

  5. Hardware Design and Security in the Era of Chiplets and LLMs

    Aug 5, 2026Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1Hardware Description LanguagesChip Design

  6. SpreadMark: Robust Image Watermarking via Spread-Spectrum Embedding

    Aug 4, 2026Wei Song, Yuxin Cao, Zhenchang Xing +4WatermarkingDeepfake Detection

  7. EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis

    Aug 2, 2026Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5Electronic Design AutomationChip Design

  8. Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair

    Jul 30, 2026Ha Trung TranFormal VerificationChip Design

  9. The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing

    Jul 27, 2026Stefan Scholze, Johannes Partzsch, Sebastian Höppner +27Neuromorphic HardwareChip Design

  10. CHiPS: Character Histograms and Positional Signals for Lightweight Authorship Attribution in Romanian Texts

    Jul 24, 2026Sanda-Maria Avram, George C. ŢurcaşAuthorshipHuman Annotators

  11. EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair

    Jul 22, 2026Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2Electronic Design AutomationChip Design

  12. LLM for EDA in Front-End Design: Challenges and Opportunities

    Jul 10, 2026Kangwei Xu, Bing Li, Ulf SchlichtmannElectronic Design AutomationHigh-Level Synthesis

  13. Self-Specializing Vision-Language Transmon Chip Calibration in a Physics-Grounded Environment

    Jul 3, 2026Animesh Tripathy, Aswanth KrishnanMulticalibration and CalibrationChip Design

  14. Agentic Hardware Design as Repository-Level Code Evolution

    Jun 26, 2026Cunxi Yu, Chenhui Deng, Nathaniel Pinckney +1Self-Evolving AgentsRepository-Level Code Understanding

  15. Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming

    Jun 21, 2026Poornima Kumaresan, Santhosh SivasubramaniNeuromorphic HardwareResistive Random Access Memory

  16. Multi-Level Resistive Synapses for On-Chip Neural Networks: A Physics-Based Design of a Memristive Crossbar Fabric with Quasi-Continuous Conductance States

    Jun 21, 2026David Alejandro Trejo PizzoResistive Random Access MemoryNeuromorphic Hardware

  17. DART: A design-aware microfluidic chip paradigm for real-time live-cell image analysis

    Jun 16, 2026Johannes Seiffarth, Matthias Pesch, Lukas Scholtes +3MicroscopyFluidic Transport

  18. LLM4RTL: Tool-Assisted LLM for RTL Generation

    Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1VhdlRegister Transfer Level

  19. SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC

    Jun 8, 2026Sonu Kumar, Akash Sankhe, Mukul Lokhande +1Sparse Deep Neural Network AcceleratorsRisc-V

  20. Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution

    Jun 8, 2026Shibing Mo, Jing Liu, Jianchu Xu +1Chip DesignOrder Matters

  21. ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs

    Jun 4, 2026Haihang Xia, Xinyu Zhao, Xuecheng Wang +5Spiking Neural NetworksSpike-Timing-Dependent Plasticity

  22. CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

    Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Flexible Register Transfer Level Design AutomationRegister Transfer Level

  23. Operator Fusion for LLM Inference on the Tensix Architecture

    Jun 3, 2026Qingbo Wu, Ke Li, Wenzhu Wang +3Tensor ProgramsSparse Deep Neural Network Accelerators

  24. StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

    Jun 2, 2026Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2VhdlFlexible Register Transfer Level Design Automation

  25. Feasibility of Time-Domain DNN-Based Speech Enhancement on Embedded FPGA for Hearing Aid

    Jun 2, 2026Feyisayo Olalere, Umut Altin, Kiki van der Heijden +1Speech EnhancementSpeech Separation

  26. UniRTL: Unifying Code and Graph for Robust RTL Representation Learning

    May 29, 2026Yi Liu, Hongji Zhang, Lei Chen +2Flexible Register Transfer Level Design AutomationRegister Transfer Level

  27. Reinforcement learning for ion shuttling on trapped-ion quantum computers

    May 21, 2026Maximilian Schier, Lea Richtmann, Christian Staufenbiel +4Quantum ComputingChip Design

  28. Mapping Tomato Cropping Systems in California Using AlphaEarth Geospatial Embeddings and Deep Learning Analysis

    May 20, 2026Mohammadreza Narimani, Alireza Pourreza, Parastoo FarajpoorFruitDeep Learning

  29. FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

    May 19, 2026Haoyi Zhang, Kairong Guo, Bojie Zhang +2Chip DesignProgressive Attention Fusion

  30. Memory-Guided Tree Search with Cross-Branch Knowledge Transfer for LLM Solver Synthesis

    May 17, 2026Fatemeh Haji, Javier Delarosa Quiros, Peyman NajafiradFuture Llm-Assisted Solver DevelopmentTree Search

  31. Physics-Guided Geometric Diffusion for Macro Placement Generation

    May 15, 2026Jongho Yoon, Jinsung Jeon, Seokhyeong KangLayoutsChip Design

  32. Variational Matrix-Learning Fourier Networks for Parametric Multiphysics Surrogates

    May 4, 2026Xinyu Li, Jianhua Zhang, Liang ChenConventional Physics-Informed Neural NetworksSurrogate Models

  33. DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams

    May 2, 2026Jincheng Lou, Ruohan Xu, Jiapeng Li +6DiagramsDiagnostic Benchmark

  34. Autoformalizing Memory Specifications with Agents

    Apr 30, 2026Jan Ole Ernst, Dmitri Michelangelo Saberi, Derek Christ +6Formal VerificationChip Design

  35. How Can Reinforcement Learning Achieve Expert-level Placement?

    Apr 28, 2026Ruo-Tong Chen, Ke Xue, Chengrui Gao +7Deep Reinforcement LearningChip Design

  36. FlowPlace: Flow Matching for Chip Placement

    Apr 26, 2026Peng Xie, Ke Xue, Yunqi Shi +6Chip DesignLayouts

  37. WarPGNN: A Parametric Thermal Warpage Analysis Framework with Physics-aware Graph Neural Network

    Mar 19, 2026Haotian Lu, Jincong Lu, Sachin Sachdeva +1Graph Neural NetworksChip Design

  38. Hybrid Event Frame Sensors: Modeling, Calibration, and Simulation

    Nov 22, 2025Yunfan Lu, Nico Messikommer, Xiaogang Xu +5Multi-Sensor FusionVision Sensors