Chip Design

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  1. From Ideas to Actions: A Public-Data Decision-Support Toolchain Across the Venture Lifecycle

    Sep 14, 2026Lei QuFinancial Strategy ResearchDecision Support

  2. A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs

    Sep 12, 2026Elia Mateu-Barriendos, Álvaro Gómez-Pau, Josep Rius +3Resistive Random Access MemorySpiking Neural Networks

  3. Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs

    Sep 3, 2026Yujie Zhang, Huiying Lan, Ehsan Aghapour +5Sparse Deep Neural Network AcceleratorsParallel

  4. LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

    Sep 3, 2026Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng +1High-Level SynthesisAnd Mixed-Signal Circuits

  5. RACE-AIMC: Selective Inference for Heterogeneous Analog In-Memory Accelerators at the Edge

    Sep 2, 2026Osama Yousuf, Martin Lueker-BodenIn-Memory ComputingAccelerator

  6. CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis

    Sep 1, 2026Ruichen Qi, Junyi Luo, Xinting Jiang +5Sparse Deep Neural Network AcceleratorsAnd Mixed-Signal Circuits

  7. Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems

    Sep 1, 2026Danial Noori Zadeh, Mohamed B. ElamienAnalog CircuitsAnd Mixed-Signal Circuits

  8. AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

    Aug 13, 2026Mohammed Ayman Habib, Rylan Hart, Morteza FayaziAnalog CircuitsCircuits

  9. Finding the Needle in a Haystack: Test-Time Analog Circuit Representation Adaptation for Bayesian Optimization

    Aug 13, 2026Fin Amin, Sounak Dutta, Paul D. FranzonBayesian OptimizationAnalog Circuits

  10. NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation

    Aug 12, 2026Jiarui Ma, Jianghan Wang, Yuheng Ma +2And Mixed-Signal CircuitsLarge Language Model Reliability

  11. ICM Out! Better Tournament Strategy from Computed Continuations, vs. Solvers and LLMs

    Aug 10, 2026Boning Li, Longbo HuangImperfect-Information GamesGame Theory

  12. Hardware Design and Security in the Era of Chiplets and LLMs

    Aug 5, 2026Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1Hardware Description LanguagesChip Design

  13. ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration

    Aug 5, 2026Osei Brempong, Mohammed Ayman Habib, Vivan Poddar +1Analog CircuitsConstrained Reinforcement Learning

  14. AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits

    Aug 4, 2026Shuo Ren, Yaohui Han, Libo Shen +4Electronic Design AutomationAnd Mixed-Signal Circuits

  15. SpreadMark: Robust Image Watermarking via Spread-Spectrum Embedding

    Aug 4, 2026Wei Song, Yuxin Cao, Zhenchang Xing +4WatermarkingDeepfake Detection

  16. Chat Debugging: An Exploratory Study of Human-AI Collaboration to Debug Analog Circuits

    Aug 3, 2026John Hu, Andrew AshPrecise DebuggingAnalog Circuits

  17. EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis

    Aug 2, 2026Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5Electronic Design AutomationChip Design

  18. Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair

    Jul 30, 2026Ha Trung TranFormal VerificationChip Design

  19. Investigating reservoir computing for branch prediction in pipelined processors using emerging CMOS memristor devices

    Jul 29, 2026Harvey Samuel George Johnson, Sendy PhangResistive Random Access MemoryReservoir Computing

  20. The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing

    Jul 27, 2026Stefan Scholze, Johannes Partzsch, Sebastian Höppner +27Neuromorphic HardwareChip Design

  21. ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits

    Jul 25, 2026Jiajun Zou, Jiawei Liu, Ao Liu +8And Mixed-Signal CircuitsCircuits

  22. CHiPS: Character Histograms and Positional Signals for Lightweight Authorship Attribution in Romanian Texts

    Jul 24, 2026Sanda-Maria Avram, George C. ŢurcaşAuthorshipHuman Annotators

  23. EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair

    Jul 22, 2026Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2Electronic Design AutomationChip Design

  24. RF-Agent: A Practical Framework for Building Language Agents for RFIC Design

    Jul 21, 2026Yueqi Xing, Houbo He, Jolie Wang +5Table Reasoning DatasetsElectronic Design Automation

  25. SPECS: Speciated Evolutionary Circuit Synthesis

    Jul 15, 2026Yağız Gençer, Stefan Uhlich, Andrea Bonetti +3Analog CircuitsTopological Data Analysis

  26. Lighthouse RL: Sample-Efficient Circuit Optimization via Strategic Reset Points

    Jul 15, 2026Mustafa Emre Gürsoy, Stefan Uhlich, Ryoga Matsuo +6Analog CircuitsDeep Reinforcement Learning

  27. Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation

    Jul 15, 2026Dimple Vijay Kochar, Hae-Seung Lee, Anantha P. ChandrakasanAnalog CircuitsAnalog

  28. EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

    Jul 15, 2026Guanglei Zhou, Chen-Chia Chang, Yikang Shen +5Analog CircuitsMonte Carlo Tree Search

  29. A 32-channel event-based bio-signal analog front-end with adaptive delta and pulse frequency encoding

    Jul 14, 2026Narayanan Shyam, Saptarshi Ghosh, Giacomo IndiveriNeuromorphic HardwareMultimodal Physiological Signals

  30. LLM for EDA in Front-End Design: Challenges and Opportunities

    Jul 10, 2026Kangwei Xu, Bing Li, Ulf SchlichtmannElectronic Design AutomationHigh-Level Synthesis

  31. SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

    Jul 6, 2026Arash Esshaghi, Siavash Es'haghi, Gholamreza Shahabadi +1And Mixed-Signal CircuitsMonte Carlo

  32. SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

    Jul 4, 2026Xunqi Li, Chris H. KimAnalog CircuitsClosed-Loop Reliability

  33. Self-Specializing Vision-Language Transmon Chip Calibration in a Physics-Grounded Environment

    Jul 3, 2026Animesh Tripathy, Aswanth KrishnanMulticalibration and CalibrationChip Design

  34. Agentic Hardware Design as Repository-Level Code Evolution

    Jun 26, 2026Cunxi Yu, Chenhui Deng, Nathaniel Pinckney +1Self-Evolving AgentsRepository-Level Code Understanding

  35. An Open-Source LFSR-Based Stochastic Leaky Integrate-and-Fire Neuron in SkyWater 130 nm: Design, Stochastic Characterisation, and Rate Coding

    Jun 22, 2026Poornima Kumaresan, Santhosh SivasubramaniNeuromorphic HardwareAnd Mixed-Signal Circuits

  36. Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming

    Jun 21, 2026Poornima Kumaresan, Santhosh SivasubramaniNeuromorphic HardwareResistive Random Access Memory

  37. Multi-Level Resistive Synapses for On-Chip Neural Networks: A Physics-Based Design of a Memristive Crossbar Fabric with Quasi-Continuous Conductance States

    Jun 21, 2026David Alejandro Trejo PizzoResistive Random Access MemoryNeuromorphic Hardware

  38. An LLM-Orchestrated Agent for Directional-Coupler Design with Self-Consistent Eigenmode and FDTD Validation

    Jun 21, 2026Saumya Biswas, Amrit De, Md Tauhidul IslamPhotonic DevicesAnalog Circuits

  39. Failure Analysis in Transition: An Industry Survey of Challenges, Priorities, and Standardization Needs in Advanced Packaging and Heterogeneous Integration

    Jun 20, 2026Himanandhan Reddy Kottur, Nusra Akter Takia, Mahamudul Hassan Fuad +3Semiconductor ManufacturingAnd Mixed-Signal Circuits

  40. DART: A design-aware microfluidic chip paradigm for real-time live-cell image analysis

    Jun 16, 2026Johannes Seiffarth, Matthias Pesch, Lukas Scholtes +3MicroscopyFluidic Transport

  41. NVMOS: Non-Verbal Vocalization Quality Assessment in Speech

    Jun 14, 2026Jialong Mai, Jinxin Ji, Xiaofen Xing +2Speaker RecognitionPerceptual Quality

  42. LLM4RTL: Tool-Assisted LLM for RTL Generation

    Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1VhdlRegister Transfer Level

  43. PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation

    Jun 13, 2026Haoyi Zhang, Weijian Fan, Xiaohan Gao +3Analog CircuitsLayouts

  44. Surveying GenAI-based Automation in Printed Circuit Board Design and Test

    Jun 10, 2026Sahana Srinivasan, Benjamin Turnbull, Hammond PearceAnd Mixed-Signal CircuitsComputer-Aided Design

  45. OpenOpt: An Open-Source SRAM Optimizer Based on Equivalent Circuit Model

    Jun 8, 2026Yikai Wang, Yiheng Wu, Can Wang +5And Mixed-Signal CircuitsVram

  46. SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC

    Jun 8, 2026Sonu Kumar, Akash Sankhe, Mukul Lokhande +1Sparse Deep Neural Network AcceleratorsRisc-V

  47. Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution

    Jun 8, 2026Shibing Mo, Jing Liu, Jianchu Xu +1Chip DesignOrder Matters

  48. ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs

    Jun 4, 2026Haihang Xia, Xinyu Zhao, Xuecheng Wang +5Spiking Neural NetworksSpike-Timing-Dependent Plasticity

  49. CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

    Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Flexible Register Transfer Level Design AutomationRegister Transfer Level

  50. Operator Fusion for LLM Inference on the Tensix Architecture

    Jun 3, 2026Qingbo Wu, Ke Li, Wenzhu Wang +3Tensor ProgramsSparse Deep Neural Network Accelerators

  51. Long-Term and Short-Term Transistor Aging in Deep Neural Networks: Impact and Mitigation

    Jun 2, 2026Alireza Sarmadi, Virinchi Roy Surabhi, Prashanth Krishnamurthy +3Graph Neural Network InferenceModern Deep Networks

  52. StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

    Jun 2, 2026Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2VhdlFlexible Register Transfer Level Design Automation

  53. Feasibility of Time-Domain DNN-Based Speech Enhancement on Embedded FPGA for Hearing Aid

    Jun 2, 2026Feyisayo Olalere, Umut Altin, Kiki van der Heijden +1Speech EnhancementSpeech Separation

  54. UniRTL: Unifying Code and Graph for Robust RTL Representation Learning

    May 29, 2026Yi Liu, Hongji Zhang, Lei Chen +2Flexible Register Transfer Level Design AutomationRegister Transfer Level

  55. Reinforcement learning for ion shuttling on trapped-ion quantum computers

    May 21, 2026Maximilian Schier, Lea Richtmann, Christian Staufenbiel +4Quantum ComputingChip Design

  56. Mapping Tomato Cropping Systems in California Using AlphaEarth Geospatial Embeddings and Deep Learning Analysis

    May 20, 2026Mohammadreza Narimani, Alireza Pourreza, Parastoo FarajpoorFruitDeep Learning

  57. FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

    May 19, 2026Haoyi Zhang, Kairong Guo, Bojie Zhang +2Chip DesignProgressive Attention Fusion

  58. Buffer-Parameterized Machine Learning Surrogate Models for Cross-Technology Signal Integrity Analysis and Optimization

    May 18, 2026Julian Withöft, Werner John, Emre Ecik +2Surrogate ModelsAnd Mixed-Signal Circuits

  59. Memory-Guided Tree Search with Cross-Branch Knowledge Transfer for LLM Solver Synthesis

    May 17, 2026Fatemeh Haji, Javier Delarosa Quiros, Peyman NajafiradFuture Llm-Assisted Solver DevelopmentTree Search

  60. Physics-Guided Geometric Diffusion for Macro Placement Generation

    May 15, 2026Jongho Yoon, Jinsung Jeon, Seokhyeong KangLayoutsChip Design