Register Transfer Level

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Period ending 2026-09-21

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Period ending 2026-09-14

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3 new papers

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  1. Trust, but Validate the Instrument: Auditing AI-Generated RTL Verification Plans on Authored Security-Regression Proxies

    Sep 17, 2026Hang Xiao, Chuhong Xu, Kainan Zhou +2Runtime EnforcementAlgorithm Auditing

  2. Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems

    Sep 9, 2026Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto +7Quantum ComputingHigh-Performance Computing

  3. LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

    Sep 3, 2026Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng +1High-Level SynthesisAnd Mixed-Signal Circuits

  4. Dictionary-Guided Mutation Operators for Automated HDL Repair

    Sep 1, 2026Maisha Mastora, Dean SullivanHardware Description LanguagesCryptographically Authorized Mutation

  5. LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow

    Aug 31, 2026Chenyang Yin, Agasthi Haputhanthri, Aditya Anirudh Jonnalagadda +7Hardware Description LanguagesFlexible Register Transfer Level Design Automation

  6. SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization

    Aug 13, 2026Fangzhou Liu, Peiyi Han, Jiawei Liu +5High-Level SynthesisAutomated Synthesis Techniques

  7. FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Trees

    Aug 12, 2026Zhiqiang Que, Chang Sun, Haiyang Wang +6Extreme Low-Bit QuantizationField-Programmable Gate Arrays

  8. Fast and Memory-Efficient Wavelet Convolutions via I/O-Aware Reformulation

    Aug 11, 2026Amit Aflalo, Shahaf E. Finder, Roy Amoyal +2ConvolutionalDiscrete Wavelet Transform

  9. RAG-Based Auto-Configuration for Industrial Fieldbus Devices

    Aug 9, 2026Aadil Gani Ganie, Saad Ezzini, Naveed Farooz MaraziIndustrialHardware Description Languages

  10. HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

    Aug 7, 2026Tairan Cheng, Yi Liu, Dongsheng Zuo +6Flexible Register Transfer Level Design AutomationRegister Transfer Level

  11. HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation

    Aug 7, 2026Yuebo Luo, Ahmad Sedigh Baroughi, Philip Stachura +4High-Level SynthesisAccelerator

  12. Hardware Design and Security in the Era of Chiplets and LLMs

    Aug 5, 2026Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1Hardware Description LanguagesChip Design

  13. VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space

    Aug 3, 2026Yu-Tung Liu, Cunxi YuVhdlFlexible Register Transfer Level Design Automation

  14. Don't Regenerate, Debug: A Domain-Specific Agent for Repairing Near-Miss Hardware Operators

    Aug 3, 2026Yansong Sun, Shenxiu Wu, Siyuan Chen +6Precise DebuggingFault Injection Experiments

  15. FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?

    Aug 2, 2026Weimin Fu, Hejia Zhang, Minghao Shao +6Hardware Description LanguagesField-Programmable Gate Arrays

  16. RTLCurator: Label-Efficient Data Curation for RTL Generation

    Jul 31, 2026Siyang Cai, Cangyuan Li, Wenjing Chang +4Flexible Register Transfer Level Design AutomationRegister Transfer Level

  17. ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents

    Jul 30, 2026Stef Cuyckens, Mihaela Jivanescu, Jun Yin +2Register Transfer LevelLarge Language Model Agents

  18. Investigating reservoir computing for branch prediction in pipelined processors using emerging CMOS memristor devices

    Jul 29, 2026Harvey Samuel George Johnson, Sendy PhangResistive Random Access MemoryReservoir Computing

  19. GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure

    Jul 28, 2026Xin Xin, Jincheng Lou, Junhui Li +11Formal VerificationRegister Transfer Level

  20. ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design

    Jul 28, 2026Jingbo Zhang, Haoxiang Sun, Wenbo Wang +1High-Level SynthesisKernel Contracts

  21. Formally Verified Synthesizable Floating-Point Data Types in ARCH HDL

    Jul 26, 2026Shuqing ZhaoFloating-PointSystematic Fp16 Divergence

  22. Benchmarking LLMs for Verilog Design Flows

    Jul 23, 2026Angshuman Chakravertty, Rahul Koshti, Buddhi Prakash Sharma +1VhdlHigh-Level Synthesis

  23. Search Hardness-Aware LLM-Based Problem Formulation for Expensive Simulation-Driven Design

    Jul 23, 2026Yuchen Li, Handing Wang, Bing Xue +1Hardware Description LanguagesLlm-Based Optimization Modeling

  24. Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows

    Jul 20, 2026Jinyuan Deng, Zhengrui Chen, Xufeng Wei +4Electronic Design AutomationWorkflow Automation and Optimization

  25. When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering

    Jul 19, 2026Ziteng Hu, Jiachi Chen, Wenhao Lv +2Hardware Description LanguagesLarge Language Models(Llms

  26. CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents

    Jul 18, 2026Peilong Zhou, Zhirong Chen, Cangyuan Li +4Flexible Register Transfer Level Design AutomationToken Budgets

  27. Automated Hardware Validation Test Plan Generation for Large Scale AI Datacenter Platforms Using a Generative AI Multi-Agents Architecture

    Jul 17, 2026Mohammed-Khalil Ghali, Saurabh Kulkarni, Prathamesh Kulkarni +3Test GenerationFault Injection Experiments

  28. RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

    Jul 17, 2026Ziyan Guo, Wenji Fang, Wenkai Li +3Sequence ModelingRegister Transfer Level

  29. Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlations

    Jul 15, 2026Wenxuan Miao, Haosong Liu, Weiming Hu +9Pre-Trained Video Diffusion ModelsAccelerator

  30. AutoVSR: Automatic Visual-to-Symbolic Reasoning for Symbolic Expression Generation from Circuit Schematic

    Jul 13, 2026Zhe Xiao, Longfei Li, Xu He +3VhdlSymbol-

  31. LLM for EDA in Front-End Design: Challenges and Opportunities

    Jul 10, 2026Kangwei Xu, Bing Li, Ulf SchlichtmannElectronic Design AutomationHigh-Level Synthesis

  32. AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance

    Jun 29, 2026Yang Zou, Zijian Ding, Yizhou Sun +1High-Level SynthesisCode Refactoring

  33. Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification

    Jun 25, 2026Zhe Zhao, Hongbing Lang, Zhihan Xiao +3High-Level SynthesisPersonalized Large Language Model Agents

  34. VeriPilot: An LLM-Powered Verilog Debugging Framework

    Jun 22, 2026Yihan Wang, Cheng Liu, Jiazheng Zhang +4VhdlPrecise Debugging

  35. AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting

    Jun 16, 2026Yiting Wang, Chenhui Deng, Chia-Tung Ho +6Flexible Register Transfer Level Design AutomationField-Programmable Gate Arrays

  36. Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement

    Jun 16, 2026You Li, Samuel Mandell, David Z. PanHardware Description LanguagesRegister Transfer Level

  37. LLM4RTL: Tool-Assisted LLM for RTL Generation

    Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1VhdlRegister Transfer Level

  38. VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation

    Jun 11, 2026Yijun Shen, Minghao Shao, Yichen Zhao +4VhdlHardware Description Languages

  39. Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation

    Jun 11, 2026En-Ming Huang, Yu-Hung Kao, Ren-Hao Deng +10Hardware Description LanguagesFlexible Register Transfer Level Design Automation

  40. OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

    Jun 9, 2026Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali +6VhdlLarge Language

  41. Spiking Neural Network inference on FPGAs with hls4ml

    Jun 8, 2026Barry M. DillonSpiking Neural NetworksField-Programmable Gate Arrays

  42. RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

    Jun 8, 2026Jing Wang, Shang Liu, Wenji Fang +3Register Transfer LevelBenchmarking Large Language Models

  43. ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards

    Jun 6, 2026Prashanth Vijayaraghavan, Charles Mackin, Luyao Shi +6VhdlHardware Description Languages

  44. CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

    Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Flexible Register Transfer Level Design AutomationRegister Transfer Level

  45. Alpha-RTL: Test-Time Training for RTL Hardware Optimization

    Jun 3, 2026Peilong Zhou, Zhirong Chen, Cangyuan Li +4Flexible Register Transfer Level Design AutomationRegister Transfer Level

  46. StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

    Jun 2, 2026Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2VhdlFlexible Register Transfer Level Design Automation

  47. HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite

    Jun 2, 2026Benjamin Goldblatt, Paolo Pedroso, Farhad Modaresi +2VhdlBenchmark Suite

  48. Foley-Omni: A Unified Multimodal Generation Model from Task-Level Audio Synthesis to Complete Video Soundtrack Generation

    Jun 2, 2026Ye Tao, Lupeng Liu, Xuenan Xu +6Joint Audio-Video GenerationMultimodal Generation

  49. EstRTL: Functional Estimation Guided RTL Code Generation

    Jun 1, 2026Qi Xiong, Renzhi Chen, Bowei Wang +3Flexible Register Transfer Level Design AutomationRegister Transfer Level

  50. UniRTL: Unifying Code and Graph for Robust RTL Representation Learning

    May 29, 2026Yi Liu, Hongji Zhang, Lei Chen +2Flexible Register Transfer Level Design AutomationRegister Transfer Level

  51. Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation

    May 26, 2026Zehua Pei, Hui-Ling Zhen, Yu Zhang +3VhdlFlexible Register Transfer Level Design Automation

  52. GoQuant: Geometric Orthogonal Residual Projection for Multiplier-Free Power-of-Two Transformer Quantization

    May 25, 2026Maoyang Xiang, Tao Luo, Bo WangQuantizationFlexible Register Transfer Level Design Automation

  53. Trace2Skill: Verifier-Guided Skill Evolution for Long-Context EDA Agents

    May 20, 2026Zijian Du, Nathaniel PinckneyVhdlElectronic Design Automation

  54. Verifier-Guided Code Translation via Meta-Step Decoding

    May 17, 2026Tianyang Zhou, Somesh Jha, Mihai Christodorescu +2Code GenerationTest-Time Scaling

  55. RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision

    May 15, 2026Jing Wang, Shang Liu, Hangan Zhou +1Flexible Register Transfer Level Design AutomationRegister Transfer Level

  56. Natural Synthesis: Outperforming Reactive Synthesis Tools with Large Reasoning Models

    May 14, 2026Frederik Schmitt, Matthias Cosler, Niklas Metzger +4Constraint-Aware SynthesisFormal Verification

  57. A3D: Agentic AI flow for autonomous Accelerator Design

    May 14, 2026Abinand Nallathambi, Christopher Knight, Shantanu Ganguly +2AcceleratorHigh-Level Synthesis

  58. HLS-Seek: QoR-Aware Code Generation for High-Level Synthesis via Proxy Comparative Reward Reinforcement Learning

    May 13, 2026Qingyun Zou, Feng Yu, Hongshi Tan +3High-Level SynthesisDeep Reinforcement Learning

  59. ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation

    May 13, 2026Zhongkai Yu, Yichen Lin, Chenyang Zhou +12Flexible Register Transfer Level Design AutomationVhdl

  60. LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

    May 11, 2026Johann Knechtel, Ozgur Sinanoglu, Ramesh KarriHardware Description LanguagesElectronic Design Automation