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Period ending 2026-09-21

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Period ending 2026-09-14

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Period ending 2026-09-07

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85 papers

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  1. CktFormalizer: Autoformalization of Natural Language into Circuit Representations

    May 8, 2026Jing Xiong, Qi Han, Chenchen Ding +4Hardware Description LanguagesVhdl

  2. Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification

    May 7, 2026Vaisakh Naduvodi Viswambharan, Keerthan Kopparam Radhakrishna, Deepak Narayan Gadde +1Formal VerificationSystemverilog Assertions

  3. LLM-Driven Design Space Exploration of FPGA-based Accelerators

    May 7, 2026Vinamra Sharma, Xingjian Fu, Jude Haris +1AcceleratorField-Programmable Gate Arrays

  4. From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation

    Apr 30, 2026Guang Yang, Xing Hu, Xiang Chen +1VhdlCode Generation

  5. RuC: HDL-Agnostic Rule Completion Benchmark Generation

    Apr 30, 2026Arnau Ayguadé Domingo, Miquel Alberti-Binimelis, Cristian Gutierrez-Gomez +5Hardware Description LanguagesSample Size

  6. MappingEvolve: LLM-Driven Code Evolution for Technology Mapping

    Apr 29, 2026Rongliang Fu, Yi Liu, Qiang Xu +1Code OptimizationHigh-Level Synthesis

  7. QASM-Eval: A Dataset to Train and Evaluate LLMs on OpenQASM-3 Beyond Quantum Circuits

    Apr 28, 2026Zhenxiao Fu, Lei Jiang, Fan ChenQuantum Circuit SimulationQuantum Computing

  8. VISION-SLS: Safe Perception-Based Control from Learned Visual Representations via System Level Synthesis

    Apr 27, 2026Antoine P. Leeman, Shuyu Zhan, Melanie N. Zeilinger +1Visual ServoingFeedback Linearization

  9. How LLMs Fail and Generalize in RTL Coding for Hardware Design?

    Apr 26, 2026Guan-Ting Liu, Chao-Han Huck Yang, Chenhui Deng +3Hardware Description LanguagesRegister Transfer Level

  10. TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

    Apr 26, 2026Armin Abdollahi, Negin Ashrafi, Mehdi Kamal +1VhdlFlexible Register Transfer Level Design Automation

  11. LEGO: An LLM Skill-Based Front-End Design Generation Platform

    Apr 25, 2026Jincheng Lou, Ruohan Xu, Jiecheng Ma +3Flexible Register Transfer Level Design AutomationBuilding Blocks

  12. ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration

    Apr 21, 2026Cagri EryilmazRegister Transfer LevelNeuro-Symbolic Framework

  13. AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning

    Apr 20, 2026Chongxiao Li, Pengwei Jin, Di Huang +14Power MethodRegister Transfer Level

  14. Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation

    Apr 18, 2026Minghao Shao, Zeng Wang, Weimin Fu +5Benchmarking Large Language ModelsLarge Language

  15. HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design

    Apr 17, 2026Shiva Ahir, Prajna Bhat, Alex DoboliHardware Description LanguagesRegister Transfer Level

  16. COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation

    Apr 16, 2026Heng Ping, Peiyu Zhang, Shixuan Li +5Register Transfer LevelHardware Description Languages

  17. Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

    Apr 16, 2026Wenji Fang, Yao Lu, Shang Liu +5Flexible Register Transfer Level Design AutomationRegister Transfer Level

  18. Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation

    Apr 16, 2026Mu-Chi Chen, Po-Hsuan Huang, Yu-Hung Kao +6VhdlHardware Description Languages

  19. VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs

    Apr 16, 2026Sazzadul Islam, Tasnim Tabassum, Hao ZhengVhdlHardware Description Languages

  20. LLM-Guided Dynamic Action Spaces for Synthesizable Molecular Optimization

    Apr 9, 2026Tao Li, Kaiyuan Hou, Tuan Vinh +4Molecular OptimizationReaction

  21. Receptogenesis in a Vascularized Robotic Embodiment

    Mar 10, 2026Kadri-Ann Pankratov, Leonid Zinatullin, Hans Priks +6Soft RobotsAdditive Manufacturing

  22. Retrieval Augmented (Knowledge Graph), and Large Language Model-Driven Design Structure Matrix (DSM) Generation of Cyber-Physical Systems

    Jan 30, 2026H. Sinan Bank, Daniel R. HerberHardware Description LanguagesComputer-Aided Design

  23. TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion

    Jan 23, 2026Saideep Sreekumar, Zeng Wang, Akashdeep Saha +6HoneypotsHardware Description Languages

  24. HardSecBench: Benchmarking the Security Awareness of LLMs for Hardware Code Generation

    Jan 20, 2026Qirui Chen, Jingxian Shuai, Shuangwu Chen +8Hardware Description LanguagesSecurity Analysis

  25. Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design

    Nov 6, 2023James T. MeechHardware Description LanguagesHigh-Level Synthesis