Electronic Design Automation

Also known as EDA

Overview

Electronic Design Automation (EDA) develops tools for turning hardware specifications into circuits, chip layouts, and printed circuit boards, then checking that designs work and meet constraints such as timing, power, area, and manufacturability. Traditional methods include logic synthesis, formal verification, physical-design heuristics, and circuit simulation; newer work adds graph neural networks, surrogate models, Bayesian optimization, and reinforcement learning to predict results or explore designs with fewer costly evaluations. Large language models are increasingly used to generate and repair RTL, create testbenches, and coordinate multi-step workflows with synthesis, simulation, and layout tools. A central challenge is ensuring that gains measured with proxies or on small benchmarks survive full tool flows and sign-off checks, especially for complex designs and long-running agent workflows.

Latest papers

CardsList

214 papers35 papers in the last four weeks, up 106% on the four weeks before. 0.2% of all new papers.

  1. MacroAgent: Regularity-Aware Macro Legalization with LLM-Agent-Designed Contour Algorithms

    Aug 24, 2026Jiaxi Jiang, Xufeng Yao, Yuxuan Zhao +5Electronic Design Automation

  2. Spicing up Genetic Netlist Generation with LLMs

    Aug 24, 2026Stefan Uhlich, Yağız Gençer, Andrea Bonetti +4Electronic Design AutomationLarge Language Model-Guided Optimization

  3. StateTune: Transforming LLM-Assisted EDA Flow Tuning into a Stateful, Closed-Loop Process

    Aug 19, 2026Kunlong Li, Shangshang Yao, Su Zheng +1Electronic Design AutomationLarge Language Model-Guided Optimization

  4. Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design

    Aug 18, 2026Marvin Castro Castro, Erick Carvajal BarbozaElectronic Design Automation

  5. PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

    Aug 13, 2026Ruogu Chen, Jie HanMacro PlacementElectronic Design Automation

  6. Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

    Aug 13, 2026Bingyang Liu, Ziming Wei, Xiaohan Gao +1Electronic Design AutomationLarge Language Model-Guided Optimization

  7. SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization

    Aug 13, 2026Fangzhou Liu, Peiyi Han, Jiawei Liu +5Large Language Model-Guided OptimizationElectronic Design Automation

  8. Finding the Needle in a Haystack: Test-Time Analog Circuit Representation Adaptation for Bayesian Optimization

    Aug 13, 2026Fin Amin, Sounak Dutta, Paul D. FranzonDeep Kernel LearningRepresentation Learning

  9. NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation

    Aug 12, 2026Jiarui Ma, Jianghan Wang, Yuheng Ma +2LLM EvaluationBenchmark Design

  10. HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

    Aug 7, 2026Tairan Cheng, Yi Liu, Dongsheng Zuo +6Electronic Design AutomationLLM-Based Program Synthesis

  11. HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation

    Aug 7, 2026Yuebo Luo, Ahmad Sedigh Baroughi, Philip Stachura +4Code TranslationLarge Language Model-Guided Optimization

  12. MicroEvo: Knowledge-Guided LLM Sampling for Efficient Microarchitecture Design Space Exploration

    Aug 6, 2026Jia Xiong, Runkai Li, Chenxu Niu +11Evolutionary OptimizationMulti-Objective Evolutionary Optimization

  13. Hardware Design and Security in the Era of Chiplets and LLMs

    Aug 5, 2026Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1Electronic Design AutomationCybersecurity

  14. OmniRouting: A Semantic-Coupled Multimodal Benchmark for Constraint-Aware Spatial Reasoning in PCB Routing

    Aug 5, 2026Taiting Lu, Kaiyuan Lin, Ziwei Dong +18Benchmark DesignElectronic Design Automation

  15. AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits

    Aug 4, 2026Shuo Ren, Yaohui Han, Libo Shen +4Electronic Design AutomationAgentic Workflows

  16. EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis

    Aug 2, 2026Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5Retrieval-Augmented GenerationElectronic Design Automation

  17. On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies

    Aug 2, 2026Yanxin Zhang, Shayne Wadle, Yuxuan Xiong +3Learning to RankElectronic Design Automation

  18. FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?

    Aug 2, 2026Weimin Fu, Hejia Zhang, Minghao Shao +6Large Language Model-Guided OptimizationElectronic Design Automation

  19. Flash-CNNCap: Capacitance Extraction via Image Mapping

    Jul 26, 2026Hector R. Rodriguez, Jiechen Huang, Wenjian YuElectronic Design AutomationConvolutional Neural Networks

  20. ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits

    Jul 25, 2026Jiajun Zou, Jiawei Liu, Ao Liu +8Graph Neural NetworksHeterogeneous GNNs

  21. Identifying Good Rules for Efficient SAT Encodings of Single-Constant Multiplication Using Machine Learning

    Jul 23, 2026Chufeng Jiang, Neng-Fa ZhouElectronic Design Automation

  22. EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair

    Jul 22, 2026Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2Electronic Design AutomationLLM Agents